1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
Aiming at reducing the ON resistance of trench-gate-type MOSFET structures by narrowing the cell distance, a large-scale shrinkage of the cell may be achieved by filling stripe-patterned gate trenches with an insulating interlayer, after removing by over-etching a part of gate polysilicon layer preliminarily filling up the gate trenches, and by arranging a stack of an N+-source layer and a P+-base layer alternately with the gate trenches.
The U.S. Pat. No. 6,916,712 describes a MOSFET based on a structure having buried insulating interlayers in trenches. A process of manufacturing the conventional MOSFET having the buried insulating interlayers in the trenches will be explained referring to FIGS. 2A to 2C, and FIGS. 3A to 3D.
First, before the trenches are formed, a P-base layer 202 is formed in a substrate by ion implantation 201 effected in the direction of normal line (FIG. 2A). Next, trenches 203 are formed, and a gate oxide film 204 and a polysilicon layer 205 are formed over the trenches 203 (FIGS. 2B, 2C). The entire surface of the polysilicon layer 205 is then etched back, to thereby leave polysilicon layers 205 which serve later as buried gate electrodes in the trenches (FIG. 3A). Buried insulating interlayers 206 are then formed in the trenches 203 (FIG. 3B).
Regions of the P-base layers 202 reserved for later formation of a back gate layer are masked with a photoresist 207, and N+-source layers 209 are formed over the P-base layers 202 by ion implantation 208 (FIG. 3C). P+-back gate layers 210 and a source electrode 211 are then formed (FIG. 3D).
In the above MOSFET having the buried insulating interlayers in the gate trenches, the polysilicon layer 205 is etched back so as to allow filling-up of the trenches 203 with the buried insulating interlayer 206. In this process, it has been necessary to form the N+-source layers 209 deeply enough, so as not to cause offset, which means that the bottom lines of N+-source layers 209 are unsuccessful to reach the level of the upper end of the polysilicon layers 205 which serve as the buried gate electrodes.
The present inventors study an avalanche operation of the above MOSFET showed, to find the following problem. This problem in the avalanche operation will be explained, referring to FIG. 4.
Since the P-base layers 202 and the N+-source layers 209 are formed as described in the above, the thickness of each of these layers is almost constant. Also since the N+-source layers 209 are formed deeply enough, so as not to cause offset with respect to the polysilicon layers 205 remained after the etch-back, so that the P-base layers 202 are formed shallow and flat.
Accordingly, due to a small thickness 302 of the P-base layers, there has been known a problem in that the base resistance along a current path 301 towards the P+-back gate layers 210 increases, and the Avalanche resistance degrades as a consequence.
In the MOSFET under the Avalanche operation, the base resistance along the current path largely affects the breakdown voltage. It is generally considered that shallower N+-source layers and deeper P-base layers may be advantageous to moderate the resistance along the path of Avalanche current, and to improve the Avalanche resistance.
In view of avoiding the above-described offset and of moderating the ON resistance, the N+-source layers are necessarily deepened. This may, however, make the P-base layers relatively shallower, so that the base resistance towards the P+-back gate layer may increase, and thereby the Avalanche resistance may degrade. On the other hand, an attempt of making the N+-source layers shallower, aimed at improving the Avalanche resistance, may not only make the N+-source layer and the gate polysilicon layer more likely to cause the offset therebetween, but also increase the ON resistance.
In short, the conventional structure has been suffering form a trade-off problem between that reduction in the ON resistance and improvement in the Avalanche resistance.
At present, there have been known a variety of proposals on the above-described, stripe-patterned, gate trench MOSFETs (see Japanese Laid-Open Patent Publication No. 2008-112936, for example).
The MOSFET having the buried insulating interlayers in the trenches described in the U.S. Pat. No. 6,916,712 has been suffering from a problem in that the Avalanche resistance degrades if the N+-source layers are made deeper, aiming at reducing the ON resistance. On the other hand, the ON resistance increases if the N+-source layers are made shallower, aiming at improving the Avalanche resistance.